IP for CAN and CAN FD

The Synective CAN 2.0/CAN FD IP core implements a complete CAN controller for integration into FPGAs and ASICs. The IP is compliant to the new ISO 11898-1:2015 standard, supporting both standard CAN and CAN FD. CAN FD is a new version of the CAN standard, where the payload is sent at a higher bitrate (up to 10 Mbit/s). The payload can also be up to 64 bytes long, compared to 8 bytes for normal CAN. The IP is available for most Xilinx, Altera, Lattice and Microsemi FPGA devices, supporting native bus interfaces like AXI, Avalon and APB. Processor integration is available for SOC type of FPGAs. The IP is designed with many features for diagnosis and CAN bus debugging, making it ideal for data loggers and similar devices. All these features can be disabled at build time, to minimize footprint for more traditional applications.
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CAN FD, both ISO and non-ISO

 
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CAN 2.0A and 2.0B

 
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Small Footprint

 
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System Bus Interfaces: AXI, Avalon, APB

 
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Common receive interface for multiple Channels

 
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Configurable Hardware Buffer Size

 
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Status Updates in Data Stream

 
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Interrupt Logic

 
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Transmit Rate Adaptation

 
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Low-Latency DMA with Interrupt Rate Adaptation

 
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Timestamps

 
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Listen Only-mode

 
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Auto Acknowledge Mode

 
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Self-Listen-Mode

 
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Single Shot Mode

 
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Separate System Bus and Core Clocks

 
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Support for Xilinx, Intel, Lattice and Microsemi FPGAs

 
CAN FD IP architecture

Want to know more?

Please contact us and describe your use case for CAN FD, what FPGA family you plan to use etc and we will get back with an as detailed answer as possible

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High Performance Embedded

Synective Labs provides high performance embedded solution to a wide range of customers, with a focus on computational and data intense problems.

FPGA/ASIC design

Synective Labs is a leading design house and consulting company within FPGA and ASIC design in the Nordic region.

IP block

The Synective CAN 2.0/CAN FD IP core implements a complete CAN controller for integration into FPGAs and ASICs.

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