Synective remains dedicated to bringing the best and most skilled consultants in RTL programming and FPGA development to the industry. As the market demands rise and the gap between the skills obtained in the educational systems and the skills required by the industry increases, Synective Labs launches an internal Trainee-program for young engineers. The objective is to improve and tune the skills of the engineers to perfectly match the need from our customers.
The mission statement is described by Program Director Gunnar Stjernberg:
“After completing the Synective Labs FPGA trainee program, the engineer shall be able to design, code and build a semi-complex FPGA system from scratch. The trainee program shall serve as a Seal of Quality, indicating the engineer has skills highly relevant for the industry.”
The Program will be carried out at Synective Labs own facilities and will target last generation FPGA hardware and industry-leading simulators and environments. Skilled FPGA professionals with long and distinguished careers will be acting as supervisors for the Trainees. The program will be individually tailored to the participant but with a firm and comprehensive curriculum at its foundations.
Skills obtained during the program includes for example:
- Design Entry (VHDL, coding styles)
- I/O-planning and constraining
- RTL Simulation (stand-alone and in VUnit)
- Place and Route (Backend)
- Timing closure and CDC
- In-system Programming and Debugging
- Use of Hard FPGA features such as Block Memory, DSP functions and PLLs
- Hard- and Softcore CPU Systems in FPGAs (SoCs)
- Gigabit Transceivers
- Standard Serial Protocols
- Machine Learning
- Version Control in an FPGA Context
The expected duration is approximately 4-6 months. During late 2021 and early 2022, Synective plans to have two initial Trainees after which the program will be officially launched, with a target to accept two or more trainees per year going forward.