Simulating Intel FPGA IP with VUnit

Author: Ahmad Zaklouta, Synective Labs AB

FPGA developers usually try to utilize vendors’ IPs as much as possible.

Even though these IPs are usually tested thoroughly by the vendor, developers need to incorporate them in their simulation to make sure that their design behaves/communicates correctly with these IPs.

Regardless of the vendors efforts to make using their IPs as straight forward as possible, simulating these IP is not as easy as using them and with Quartus, it could actually be a tricky process.

We took the effort to automate this process and hide all the complexity and this blog will show you how to incorporate Intel FPGA IP in VUnit simulation.

The main task behind simulating an IP is to determine the required files/libraries for the IP and then add them to VUnit. For this, we will be taking advantage of Quartus tools to do most of the work. The tasks required for simulating Intel FPGA IPs are as following:

  1. Generate the IPs simulation files using Quartus tools.
  2. Generate the support-logic using Quartus compile flow.
  3. Compiling the Intel device libraries using the simulator of choice and add them to VUnit as external libraries.
  4. Generate the IPs simulation setup scripts using Quartus tools.
  5. Extract the required HDL/memory files for the IPs simulation and create a compile order file.
  6. Add files from the compile order file to Vunit library and copy the memory files to the simulator lunch directory.

These tasks are automated using the following scripts:

    • tcl/generate_project_ip_files.tcl for tasks 1 to 4.
    • tcl/create_quartus_compile_order.tcl for task 5.
    • for task 6.

Download all the example files here (zip)

INTERFACE: defines a function “add_quartus_ips” which is your interface for adding Intel FPGA IP in your VUnit python runner.

add_quartus_ips(vunit_obj, simulation_dir_path, quartus_project_file, simulator=None,  ip_generation=’yes’, support_logic=’no’,  standard_lib=’no’, sim_lang=’verilog’)


Add and compile, if necessary, all Quartus project IPs to VUnit project.

– All files are added and compiled to quartus_lib

vunit_objVUnit object passed from VUnit python runner.
simulation_dir_pathpath to the simulation directory <string>.
quartus_project_filefull path to Quartus project file *.qpf.

Simulator name, only ModelSim and QuestaSim are supported for now.

– Default is None, simulator is fetched from SIMULATOR_FACTORY.


Run Quartus ip_generation <‘yes’/’no’>.

– Default is ‘yes’, Quartus IPs must be generated for simulation either from Quartus or here.


Run Quartus support_logic Generation <‘yes’/’no’>

– Default is ‘no’, some Quartus IP like f-tile needs support_logic Generation for creating the simulation model.


Compile Quartus standard libraries <‘yes’/’no’>.

– Default is ‘no’, it is recommended to compile the libraries separately and add them in python runner as this process might take too long time.


Simulation language for Quartus IPs and standard libraries <‘verilog’/’vhdl’>.

– Default is ‘verilog’, verilog is recommended.
– Don’t confuse this with your testbench simulation language, this is just for Intel FPGA IPs and standard libraries.

Return: this function return the elaboration option for ModelSim/QuestaSim that should be used with set_sim_option(“modelsim.vsim_flags”)

– The elaboration options are extracted from the IPs simulation setup script.


This function will create a directory “quartus” in “simulation_dir_path” that contains the following:

  • quartus_ip_simulation_files.txt: This file contains a list of all required HDL files for simulating Intel FPGA IPs.
  • quartus_ip_memory_files.txt: This file contains a list of all required memory files for simulating Intel FPGA IPs.
  • If standard_lib = yes:
    • verilog_lib: this directory contains the compiled Intel device verilog standard libraries.
    • vhdl_lib: this directory contains the compiled Intel device vhdl standard libraries.


  • Quartus must be available in the PATH environment variable.
  • ModelSim/QuestaSim must be available in the PATH environment variable.
  • tcl folder must be in the same level of
  • import in your VUnit python runner.


The vunit_quartus project is a simple demonestration project that uses the LPM_COUNTER Intel FPGA IP.

In the vunit python runner, we use the add_quartus_ips function as follow:

# Simulation path

SIM_PATH = ROOT / “sim”

# Quartus project path

quartus_project = ROOT / “build”

quartus_project_file = str(Path(quartus_project) / “vunit_quartus.qpf”)

# create vunit object

VU = VUnit.from_argv()

# add Quartus IPs to vunti

elab_option = add_quartus_ips(VU, SIM_PATH, quartus_project_file, simulator=None, ip_generation=’yes’, support_logic=’no’, standard_lib=’yes’, sim_lang=’verilog’)


> python -g

Tested with Quartus Prime Pro 21.4 and QuestaSim on a Windows 10 machine.


If you have any questions or suggestions, don’t hesitate to send me an email at


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