The Synective CAN 2.0/CAN FD IP core implements a complete CAN controller for integration into FPGAs and ASICs.
The IP is compliant to the new ISO 11898-1:2015 standard, supporting both standard CAN and CAN FD. CAN FD is a new version of the CAN standard, where the payload is sent at a higher bitrate (up to 10 Mbit/s). The payload can also be up to 64 bytes long, compared to 8 bytes for normal CAN.
The IP is available for most Xilinx, Altera, Lattice and Microsemi FPGA devices, supporting native bus interfaces like AXI, Avalon and APB. Processor integration is available for SOC type of FPGAs.
The IP is designed with many features for diagnosis and CAN bus debugging, making it ideal for data loggers and similar devices. All these features can be disabled at build time, to minimize footprint for more traditional applications.